Analysis of layout and routing methods for mixed-signal PCB design

- Nov 29, 2019-

Analysis of layout and routing methods for mixed-signal PCB design

Summary of content: The operation of analog circuits depends on continuously changing currents and voltages. The operation of digital circuits depends on the detection of high or low levels at the receiving end according to a predefined voltage level or threshold, and the operation of analog circuits depends on continuously changing currents and voltages. The work of the digital circuit relies on the detection of the high or low level at the receiving end according to a predefined voltage level or threshold, which is equivalent to judging the logic state as "true" or "false". Between the high and low levels of a digital circuit, there is a "gray" area where digital circuits sometimes exhibit analog effects, such as when a digital signal transitions from a low level to a high level (state). If the transition speed is fast enough, overshoot and ringback reflection will occur. For modern board design, the concept of mixed-signal PCBs is vague, because even in pure "digital" devices, there are still analog circuits and analog effects. Therefore, in the initial design stage, in order to reliably achieve strict timing allocation, it is necessary to simulate the simulation effect. In fact, in addition to communication products that must have years of trouble-free reliability, mass-produced low-cost / high-performance consumer products require simulation of simulation effects.


Another difficulty in modern mixed-signal PCB design is the increasing number of different digital logic devices, such as GTL, LVTTL, LVCMOS, and LVDS logic. Each logic circuit has different logic thresholds and voltage swings. However, these different logic thresholds The circuit and voltage swing must be designed on a PCB. Here, you can master successful strategies and techniques by thoroughly analyzing the layout and routing design of high-density, high-performance, mixed-signal PCBs.



Basics of Mixed Signal Circuit Wiring


When digital and analog circuits share the same components on the same board, the layout and wiring of the circuit must be particular about the method.


In mixed-signal PCB design, there are special requirements for power supply traces and the isolation of analog noise and digital circuit noise from each other to avoid noise coupling. As a result, the complexity of layout and routing increases. The special requirements for power transmission lines and the requirements for isolating noise coupling between analog and digital circuits have further increased the complexity of layout and routing of mixed-signal PCBs.


If the power of the analog amplifier in the A / D converter and the digital power of the A / D converter are connected together, it is likely to cause the interaction between the analog and digital circuits. Perhaps, due to the location of the input / output connectors, the layout must mix the wiring of digital and analog circuits.


Before placing and routing, engineers need to figure out the basic weaknesses of the placement and routing scheme. Even with false judgments, most engineers tend to use placement and routing information to identify potential electrical effects.


Layout and routing of modern mixed-signal PCBs


The following will explain the mixed-signal PCB layout and routing technology through the design of the OC48 interface card. OC48 stands for Optical Carrier Standard 48, which is basically oriented to 2.5Gb serial optical communication. It is one of the high-capacity optical communication standards in modern communication equipment. The OC48 interface card contains several typical mixed-signal PCB layout and routing problems. The layout and routing process will indicate the order and steps to solve the mixed-signal PCB layout solution.


The OC48 card contains an optical transceiver for bidirectional conversion of optical signals and analog electrical signals. Analog signal input or output digital signal processor. The DSP converts these analog signals into digital logic levels, which can be connected to the microprocessor, programmable gate array, and the system interface circuit of the DSP and microprocessor on the OC48 card. . Independent phase-locked loops, power filters, and local voltage references are also integrated.


Among them, the microprocessor is a multi-power device, the main power is 2V, and the 3.3V I / O signal power is shared by other digital devices on the board. Independent digital clock source provides clock for OC48I / O, microprocessor and system I / O.


After checking the layout and wiring requirements of different functional circuit blocks, a 12-layer board is initially suggested, as shown in Figure 3. The configuration of the microstrip and stripline layers can safely reduce the coupling of adjacent trace layers and improve impedance control. A ground plane between the first and second layers will isolate the wiring of sensitive analog reference sources, CPU cores, and PLL filter power supplies from the microprocessor and DSP devices on the first layer. The power and ground planes always appear in pairs, just like what the OC48 card does to share a 3.3V power plane. This will reduce the impedance between the power supply and ground, thereby reducing noise on the power supply signal.


Avoid running digital clock lines and high-frequency analog signal lines near the power plane. Otherwise, noise from power signals will be coupled to sensitive analog signals.


According to the needs of digital signal wiring, carefully consider the use of power and analog ground plane splits, especially at the input and output of mixed-signal devices. Traversing an opening in an adjacent signal layer can cause impedance discontinuities and poor transmission line loops. These can cause signal quality, timing, and EMI issues.


Sometimes adding several ground layers, or using several peripheral layers for a local power layer or ground layer under a device, can eliminate the opening and avoid the above problems. Multiple ground layers are used on the OC48 interface card. Keeping the stacking symmetry of the opening layer and the wiring layer position can avoid card deformation and simplify the manufacturing process. As the 1 oz copper clad board has a strong ability to withstand large currents, the 3.3V power supply layer and the corresponding ground plane should use 1 oz copper clad board, and the other layers can use 0.5 oz copper clad board. Voltage fluctuation.


If you are designing a complex system from the ground plane up, you should use 0.093-inch and 0.100-inch cards to support the wiring layer and the ground isolation layer. The thickness of the card must also be adjusted according to the dimensions of the via pads and the wiring characteristics of the holes, so that the aspect ratio of the diameter of the drilled hole to the thickness of the finished card does not exceed the aspect ratio of the metallized hole provided by the manufacturer.


If you are designing a low-cost, high-yield commercial product with a minimum number of wiring layers, carefully consider the wiring details of all special power supplies on the mixed-signal PCB before placing or routing. Before starting the placement and routing, have the target manufacturer review the preliminary layering scheme. Basically, the layering should be based on the thickness of the finished product, the number of layers, the weight of copper, the impedance (with tolerances), and the minimum via pad and hole size. The manufacturer should provide a layering recommendation in writing.


It is recommended to include all controlled impedance stripline and microstrip configuration examples. Consider your impedance predictions with the manufacturer's impedances, and then use these impedance predictions to verify signal routing characteristics in simulation tools used to develop CAD routing rules.


OC48 card layout


The high-speed analog signals between the optical transceiver and the DSP are very sensitive to external noise. Similarly, all special power and reference voltage circuits create a large amount of coupling between the card's analog and digital power transmission circuits. Sometimes, limited by the shape of the case


System has to design high-density boards. Because the orientation of the external optical cable access card and the size of some components of the optical transceiver are relatively high, the position of the transceiver in the card is largely fixed. System I / O connector locations and signal assignments are also fixed. This is the basic work that must be done before the layout.


As with most successful high-density analog placement and routing schemes, to meet the layout requirements, the placement and routing requirements must be balanced. For the analog part of a mixed-signal PCB and a local CPU core with a 2V operating voltage, it is not recommended to use the layout before wiringmethod. For the OC48 card, the part of the DSP analog circuit that contains the analog reference voltage and the analog power supply bypass capacitor should be interactively routed first. After the wiring is completed, the entire DSP with analog components and wiring should be placed close enough to the optical transceiver to fully ensure that the wiring length of high-speed analog differential signals to the DSP is the shortest, and the bending and vias are minimal. The differential placement and routing symmetry will reduce the effects of common mode noise. However, it is difficult to predict the best placement solution before routing.


Consult the chip distributor's design guidelines for the PCB layout. Communicate fully with the distributor's application engineer before designing according to the guidelines. Many chip distributors have strict time limits for providing high-quality layout recommendations. Sometimes, the solutions they provide are feasible for "first-tier customers" using the device. In the area of signal integrity (SI) design, the signal integrity design of new devices is particularly important. Based on the distributor's basic guidelines and combined with the specific requirements of each power and ground pin in the package, layout and routing of the OC48 card with integrated DSP and microprocessor can begin.


After the location and wiring of the high-frequency analog part is determined, the remaining digital circuits can be placed in accordance with the grouping method shown in the block diagram. Pay attention to carefully designing the following circuits: the location of the PLL power filter circuit in a CPU with high sensitivity to analog signals; the local CPU core voltage regulator; and the reference voltage circuit for a "digital" microprocessor.


The electrical and manufacturing guidelines for digital wiring are now properly applied to the design. The foregoing design of the signal integrity of high-speed digital buses and clock signals reveals some special wiring topology requirements for processor buses, balanced Ts, and delay matching of some clock signal wiring. But you may not know, and some people have proposed an update, that is, to increase the number of termination resistors.


In the course of solving the problem, it is a matter of course to make some adjustments in the layout stage. However, before starting the wiring, it is important to verify the timing of the digital parts according to the layout. At this moment, a complete DFM / DFT layout review of the board will help ensure that the card meets the needs of the customer.


Digital wiring for OC48 card


For digital device power lines and the digital portion of mixed-signal DSPs, digital routing starts with SMD escape patterns. Use the shortest and widest print lines allowed by the assembly process. For high-frequency devices, the printed wiring of the power supply is equivalent to a small inductor, which will worsen the power supply noise and cause unwanted coupling between analog and digital circuits. The longer the power trace, the greater the inductance.


Using digital bypass capacitors can get the best layout and routing scheme. In short, fine-tune the position of the bypass capacitor as needed to make it easy to install and distribute around the digital parts and digital parts of mixed-signal devices. Use the same "shortest and widest traces" method to route the bypass capacitor circuit diagram.


When the power branch is to pass through a continuous plane (such as the 3.3V power plane on the OC48 interface card), the power pin and the bypass capacitor themselves do not have to share the same exit map to get the lowest inductance and ESR bypass. On mixed-signal PCBs such as the OC48 interface card, special attention should be paid to the wiring of the power branch. Remember to place additional bypass capacitors in a matrix arrangement on the entire card, even near passive components


After the power outlet map is determined, you can start the automatic wiring. The ATE test contacts on the OC48 card are defined during logic design. Make sure ATE reaches 100% of the nodes. In order to implement the ATE test with the smallest ATE test probe of 0.070 inches, the position of the breakout via must be reserved to ensure that the power supply layer is not interrupted by the antipads crossing of the via.


If a power and ground plane split scheme is to be used, a layer bias should be selected on adjacent wiring layers parallel to the opening. Define the forbidden wiring area on the adjacent layer according to the perimeter of the opening area to prevent wiring from entering. If the wiring must pass through the open area to another layer, make sure that the other layer adjacent to the wiring is a continuous ground layer. This will reduce the reflection path. Passing the bypass capacitor across the open power plane is good for some digital signal layouts, but it is not recommended to bridge between the digital and analog power planes because noise is coupled to each other through the bypass capacitor.


Several of the latest autorouting applications are capable of routing high-density multilayer digital circuits. In the initial wiring stage, use a 0.050-inch large-sized via pitch in the SMD exit and consider the type of package used. In the subsequent wiring stage, allow the positions of the vias to be closer to each other, so that all tools can achieve the highest routing rate. And the lowest number of vias. Because the OC48 processor bus uses an improved star topology, it has the highest priority during auto-routing.


to sum up


After the OC48 card board is completed, a signal integrity check and timing simulation are performed. The simulation proves that the wiring guidance meets the expected requirements and improves the timing index of the second layer bus. Finally, the design rule check, final manufacturing review, photomask, and review are issued to the manufacturer, and then the board layout task is officially completed

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