Analysis of the role of PCB layered stack design in suppressing EMI
Summary of content: There are many ways to solve EMI problems. Modern EMI suppression methods include: using EMI suppression coatings, selecting appropriate EMI suppression parts, and EMI simulation design. This article starts from the most basic PCB layout, discusses the role and design skills of PCB layered stacking in controlling EMI radiation.
Reasonably placing a capacitor with an appropriate capacity near the power supply pin of the IC can make the output voltage of the IC jump faster. The problem does not end there, however. Due to the limited frequency response of the capacitor, this makes it impossible for the capacitor to generate the harmonic power required to cleanly drive the output of the IC over the entire frequency band. In addition, the transient voltages formed on the power bus will form a voltage drop across the inductance of the decoupling path. These transient voltages are the main source of common-mode EMI interference. How should we solve these problems?
As far as the IC on our circuit board is concerned, the power layer around the IC can be regarded as an excellent high-frequency capacitor, which can collect the part of the energy leaked by the discrete capacitor that provides high-frequency energy for clean output. In addition, the inductance of a good power layer should be small, so that the transient signal synthesized by the inductor is also small, which reduces the common-mode EMI.
Of course, the connection from the power supply layer to the IC power pin must be as short as possible, because the rising edge of the digital signal is getting faster and faster, it is best to connect directly to the pad where the IC power pin is located, which must be discussed separately.
In order to control common-mode EMI, the power plane must help decoupling and have a sufficiently low inductance. This power plane must be a fairly well designed power plane pair. Someone may ask, to what extent is it good? The answer to the question depends on the layering of the power supply, the materials between the layers, and the operating frequency (a function of IC rise time). In general, the power layer spacing is 6mil, and the interlayer is FR4 material, so the equivalent capacitance per square inch of the power layer is about 75pF. Obviously, the smaller the interlayer distance, the greater the capacitance.
There are not many devices with a rise time of 100 to 300 ps, but according to the current development speed of IC, devices with a rise time in the range of 100 to 300 ps will occupy a high proportion. For circuits with rise times of 100 to 300 ps, 3 mil layer spacing is no longer applicable for most applications. At that time, it was necessary to use a layering technique with a layer spacing of less than 1 mil and replace the FR4 dielectric material with a material with a high dielectric constant. Now, ceramics and ceramics can meet the design requirements of 100 to 300 ps rise time circuits.
Although new materials and methods may be adopted in the future, for today's 1 to 3 ns rise time circuits, 3 to 6 mil layer spacing, and FR4 dielectric materials, it is usually sufficient to handle high-end harmonics and keep transient signals low enough, that is The common-mode EMI can be reduced very low. The PCB layering design example given in this article will assume a layer spacing of 3 to 6 mils.
From the perspective of signal traces, a good layering strategy should be to place all signal traces on one or more layers, which are next to the power or ground layers. For power supply, a good layering strategy should be that the power layer is adjacent to the ground layer, and the distance between the power layer and the ground layer is as small as possible. This is what we call the "layering" strategy.
What kind of stacking strategy can help shield and suppress EMI? The following layered stacking scheme assumes that the power supply current flows on a single layer, and single or multiple voltages are distributed in different parts of the same layer. The case of multiple power planes is discussed later.
There are several potential problems with the 4-layer board design. First, with a traditional four-layer board with a thickness of 62 mils, even if the signal layer is on the outer layer and the power and ground layers are on the inner layer, the distance between the power and ground layers is still too large.
If the cost requirement is the first priority, the following two alternatives of traditional 4-layer boards can be considered. Both of these solutions can improve the performance of EMI suppression, but they are only applicable to the situation where the component density on the board is low enough and there is sufficient area around the component (place the required copper copper layer for the power supply).
The first is the preferred solution. The outer layers of the PCB are ground layers, and the middle two layers are signal / power layers. The power supply on the signal layer is routed with wide wires, which can make the path impedance of the power supply current low and the impedance of the signal microstrip path low. From an EMI control perspective, this is the best 4-layer PCB structure available. The outer layer of the second scheme uses power and ground, and the middle two layers use signals. Compared with the traditional 4-layer board, this solution has a smaller improvement, and the interlayer impedance is not as good as the traditional 4-layer board.
If you want to control the trace impedance, the above stacking schemes must be very careful to arrange the traces under the power and ground copper islands. In addition, copper islands on power or ground planes should be interconnected as much as possible to ensure DC and low frequency connectivity.
If the component density on the 4-layer board is relatively large, it is better to use the 6-layer board. However, some stacking schemes in the 6-layer board design are not good at shielding electromagnetic fields, and have little effect on reducing transient signals of power buses. Two examples are discussed below.
In the first example, the power supply and ground are placed on the second and fifth layers, respectively. Due to the high copper impedance of the power supply, it is very unfavorable to control common mode EMI radiation. However, from the viewpoint of signal impedance control, this method is very correct.
In the second example, the power supply and the ground are placed on the third and fourth layers, respectively. This design solves the problem of copper resistance of the power supply. Due to the poor electromagnetic shielding performance of the first and sixth layers, the differential mode EMI increases. If the number of signal lines on the two outer layers is minimal and the trace length is short (shorter than 1/20 of the highest harmonic wavelength of the signal), then this design can solve the problem of differential mode EMI. The component-free and trace-free areas on the outer layer are copper-filled and the copper-clad area is grounded (at intervals of 1/20 wavelength), and the suppression of differential mode EMI is particularly good. As mentioned earlier, connect the copper area to the internal ground plane at multiple points.
The general high-performance 6-layer board design generally arranges the first and sixth layers as ground layers, and the third and fourth layers run power and ground. Since there are two middle microstrip signal line layers between the power layer and the ground layer, the EMI suppression ability is excellent. The disadvantage of this design is that there are only two trace layers. As mentioned earlier, if the outer layer traces are short and copper is laid in areas without traces, the same stacking can also be achieved with traditional 6-layer boards.
Another 6-layer board layout is signal, ground, signal, power, ground, and signal, which can achieve the environment required for advanced signal integrity design. The signal layer is adjacent to the ground layer, and the power and ground layers are paired. Obviously, the disadvantage is the imbalanced stacking of layers.
This usually brings trouble to the manufacturing. The solution to the problem is to fill all the blank areas of the third layer with copper. After the copper is filled, if the copper density of the third layer is close to the power layer or the ground layer, this board can not be strictly regarded as a structurally balanced circuit board. . The copper filling area must be connected to power or ground. The distance between the connection vias is still 1/20 the wavelength, and it is not necessary to connect everywhere, but ideally they should be connected.
Because the insulation isolation layer between the multilayer boards is very thin, the impedance between the 10 or 12 layers of circuit boards is very low. As long as there is no problem with layering and stacking, excellent signal integrity can be expected. It is more difficult to manufacture 12-layer boards with a thickness of 62 mil, and there are not many manufacturers capable of processing 12-layer boards.
Because there is always an insulation layer between the signal layer and the circuit layer, the solution of assigning the middle 6 layers to the signal lines in the 10-layer board design is not the best. In addition, it is important to make the signal layer adjacent to the loop layer, that is, the board layout is signal, ground, signal, signal, power, ground, signal, signal, ground, signal.
This design provides a good path for signal current and its loop current. The proper wiring strategy is that the first layer runs in the X direction, the third layer runs in the Y direction, the fourth layer runs in the X direction, and so on. Looking at the wiring intuitively, the first layer 1 and the third layer are a pair of layered combinations, the fourth layer and the seventh layer are a pair of layered combinations, and the 8th and 10th layers are the last pair of layered combinations. When it is necessary to change the routing direction, the signal lines on the first layer should be changed to the third layer by "vias". In fact, this may not always be possible, but as a design concept, it is still necessary to adhere to it.
Similarly, when the signal's routing direction changes, via holes should be used from the 8th and 10th layers or from the 4th to the 7th layer. This routing ensures the tightest coupling between the forward path of the signal and the loop. For example, if the signal is routed on layer 1, and the loop is routed on layer 2 and only on layer 2, then the signal on layer 1 is transferred to layer 3 even through a "via". The loop is still on the second layer, thus maintaining the characteristics of low inductance, large capacitance, and good electromagnetic shielding performance.
What if the actual routing is not the case? For example, the signal line on the first layer passes through the via to the tenth layer. At this time, the loop signal has to look for the ground plane from the ninth layer, and the loop current must find the nearest ground via (such as the ground pin of a resistor or capacitor) . If such a via happens to be nearby, it's really lucky. If no such via is available, the inductance will increase, the capacitance will decrease, and EMI will increase.
When the signal line must leave the current pair of wiring layers to other wiring layers through the via, a ground via should be placed next to the via, so that the loop signal can return to the proper ground layer smoothly. For the layered combination of layers 4 and 7, the signal loop will return from the power or ground layer (ie, the 5 or 6 layer), because the capacitive coupling between the power and ground layers is good, and the signal is easy to transmit.
Design of multiple power planes
If two power planes of the same voltage source need to output large current, the circuit board should be arranged into two sets of power planes and ground planes. In this case, an insulation layer is placed between each pair of power and ground planes. This gives us the two pairs of equal equal impedance power buses that divide the current. If the power supply layers are stacked to cause unequal impedance, the shunt will be uneven, the transient voltage will be much larger, and the EMI will increase sharply.
If there are multiple power supply voltages with different values on the circuit board, multiple power supply layers are required accordingly. Remember to create separate power supply and ground layers for different power supplies. In both cases, keep in mind the manufacturer's requirements for a balanced structure when determining where the mating power and ground planes are on the board.
to sum up
In view of the fact that the circuit boards designed by most engineers are traditional printed circuit boards with a thickness of 62 mils and no blind or buried holes, the discussion of layering and stacking of circuit boards in this article is limited to this. For circuit boards with large thickness differences, the layering scheme recommended in this article may not be ideal. In addition, the processing process of circuit boards with blind or buried holes is different, and the layering method in this article is not applicable.
The thickness of the circuit board design, the via process and the number of layers of the circuit board are not the key to solving the problem. Good layered stacking is to ensure the bypass and decoupling of the power bus and minimize the transient voltage on the power layer or ground layer. The key to shielding the signal and the electromagnetic field of the power supply. Ideally, there should be an insulating isolation layer between the signal trace layer and its return ground layer. The distance between the paired layers (or more than one pair) should be as small as possible. According to these basic concepts and principles, we can design a circuit board that always meets the design requirements. Now that the rise time of ICs has been short and will be shorter, the techniques discussed in this article are essential to solving the EMI shielding problem.