Hardware circuit design of PCB testing machine based on FPGA

- Apr 23, 2020-

Hardware circuit design of PCB testing machine based on FPGA

The basic test principle of the PCB light board test machine is Ohm's law. The test method is to add a certain test voltage between the points to be tested, and use the decoding circuit to select the two points to be tested on the PCB board to obtain the voltage corresponding to the resistance value between the two points. The signal, through the voltage comparison circuit, tests the resistance or continuity between the two points. Repeat the above steps many times to test the entire circuit board.

Because there are more points to be tested, the general test machine is more than 2048 points, the test control circuit is more complicated, the test point search method and switching method directly affect the test machine test speed, this article studies the FPGA-based hardware control system design.

Hardware control system

The test process is to control the test circuit to open different test switches under the control of the host computer. The tester system consists of the following parts: the host computer PC104, test control logic (implemented by FPGA), and high-voltage test circuit. Among them, the host computer mainly completes the functions of human-computer interaction, test algorithm, test data processing and control output. The FPGA controls the high-voltage test circuit to complete the test process of the PCB.

This system takes a PC104 as the upper computer and FPGA as the core, and realizes the control of the upper computer through the PC104 bus to the test.

The overall block diagram of the test system is shown in Figure 1.

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Interface circuit between FPGA and PC104

The PC104 bus is an industrial control bus defined specifically for embedded control. Its signal definition is basically the same as the ISA bus. The PC104 bus has 4 types of bus cycles, namely 8-bit bus cycle, 16-bit bus cycle, DMA bus cycle and refresh bus cycle. The 16-bit I / O bus cycle is 3 clock cycles, and the 8-bit I / O bus cycle is 6 clock cycles. In order to improve the communication speed, the ISA bus adopts 16-bit communication mode, that is, 16-bit I / O mode. In order to make full use of the resources of PC104, the system bus of PC104 is extended to configure the FPGA online. Data communication with FPGA through PC104 bus during normal operation.

Interface between FPGA and serial A / D and D / A devices

According to the test machine system design requirements, the test voltage and the two-channel reference voltage need to be self-checked, that is, there are at least three A / D conversion channels. The reference voltage of the two-way comparison circuit is output by D / A, then the D / A channel of the system requires two channels. In order to reduce the number of control signal lines of A / D and D / A, select serial A / D and D / A devices. Comprehensive performance, price and other factors, the selected A / D device is TLC2543, and the D / A device is TLV5618.

TLV5618 is TI's dual 12-bit voltage output DAC with buffered reference input (high impedance), and digital control is realized through a CMOS compatible 3-wire serial bus. The device receives a 16-bit command word and generates two D / A analog outputs. The TLV5618 has only a single I / O cycle, which is determined by the external clock SCL K. It continues for 16 clock cycles, writes the command word into the on-chip register, and performs D / A conversion after completion. The TLV5618 read command word is valid from the falling edge of CS. The data is read in from the falling edge of the next SCLK. After the 16-bit data is read, the conversion cycle is entered until the next falling edge of CS. Its operation timing chart is shown in Figure 2.

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TLC2543 is a 12-bit, switched capacitor successive approximation type A / D converter with serial control and 11 inputs from TI. The on-chip converter has the characteristics of high speed, high precision and low noise. The working process of TLC2543 is divided into two cycles: I / O cycle and conversion cycle. The I / O cycle is determined by the external clock SCLK, which continues for 8, 12, or 16 clock cycles, and performs two operations at the same time: input 8-bit data to the on-chip register in MSB mode on the rising edge of SCLK; output in MSB mode on the falling edge of SCLK 8, 12, 16 conversion results. The conversion cycle begins on the last SCLK falling edge of the I / O cycle until the EOC signal goes high, indicating that the conversion is complete. In order to be consistent with the I / O cycle of TLV5618, the MSB method is adopted, and the timing of CS 16 clock transmission is used. Its operation timing is shown in Figure 3.

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Because these two devices are SPI interfaces, you can connect the two devices to the same SPI bus and operate different devices through different chip select signals. Because the SPI interface protocol is complex, and as can be seen from Figure 3, the timing of these two devices does not use all the SPI interface timing. In order to realize the timing that conforms to the above logic and reduce the waste of FPGA resources on the standard SPI interface IP, the design uses Verilog hardware description language to implement the design method of synchronous state machine (FSM), and writes the ADC and DAC control timing. The program is actually a nested state machine. The master state machine and the slave state machine form a finite state machine with different functions under different input signals through the bus started by the control line. It can be seen from Figure 3 that D / A operation has 4 states, and A / D operation has 7 states. Several of the two states are the same, so a finite state machine can be used to complete the serial A / D and D / A operations. The program is actually a nested state machine. The master state machine and the slave state machine form a more complex finite state machine with different functions under different input signals through the bus started by the control bus. A / D and D / A operations share a unique drive clock (SCLK) and data bus (SI, SO). Since the write cycle of the operation has 16 clock cycles and the read cycle has 12 clock cycles, the module is completed in three nested finite state machines. The state of its main state machine is shown in Figure 4.

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In the system design, the AD and DA operations are packaged into a single module. The upper control module outputs command words and control signals to start the corresponding operation of the module. After the operation is completed (entering the idle state), the module sends the corresponding status signal to the upper module.

 

FPGA programming framework

FPGA on-chip program is the key to the correct operation of the entire test system. Based on top-down FPGA design principles, the system is divided into 5 independent modules, namely communication module (ISA), test module (TEST), AD / DA module, decoding module (DECODER), RAM control module (RAMCTL) .

ISA module: system communication and control module, complete communication with upper computer, command word interpretation, control signal generation, etc. The system starts the ADDA module to complete the output of the reference voltage according to the parameters such as the on-resistance and insulation voltage transmitted by the host computer; it starts the test module according to the test command to complete the test process. Data is transferred between multiple synchronous state machines running synchronously. What is more difficult to control is data communication and data synchronization between multiple processes.

RAM control module: Before the test starts, the host computer transmits the information of the test point to the ISA module through the bus, and the ISA module stores it in the on-chip RAM; after the test is completed, the test results in the RAM are transferred to the host computer. During the test, the test module turns on the corresponding test switch by reading the information of the test point in the RAM, and then saves the test result in the RAM. In this way, both modules require reading and writing RAM to achieve data sharing between the two modules. This requires a control signal to connect the two sets of reading and writing signal lines to the RAM module respectively. The RAM control module completes this function. Test module (TEST): Although there are various test processes, such as switch card self-test, continuity test, and insulation test, the test process is the same, that is, test scanning. The working process of the test is: add the reference voltage of the comparison circuit turn on the switch of the point to be tested delay read the result of the comparator test another set of test points. This module enters different testing processes according to different operation codes. The test result and the test point number together form 13-bit data to save in RAM, and overwrite the original test point number information.

Decoding module (DECODER): This module is hung after the test module (TEST), it completes the mapping of the switch number to the actual circuit. Due to different test pin array forms and different hardware designs of the decoding circuit and the control circuit, the test switch information output by the superior module cannot be directly used as the output control test switch circuit. The decoding module completes the conversion between the two.

AD / DA module (AD / DA): Design the SPI bus interface to operate the A / D and D / A devices. The module starts with the allowable (adenable, daenable) signal and uses the busy signal as the conversion completion flag signal. D / A operation is encapsulated relative to other modules. Each module of the system is written in Verilog hardware description language, and multiple multi-level nested synchronous state machines (FSM) are used to complete the logic functions of the entire system; each module uses the simulation tool Modelsim to complete the functional simulation of the module, and the system completes the functional test After; use Altera integrated wiring tool QuartusII to complete the system simulation, synthesis, wiring, and download; make full use of the IPcore provided by Altera Corporation to optimize the program module; the top-level design uses the block diagram input method, and the data flow between the modules is more intuitive from the block diagram Show it.

Conclusion

FPGA-based PCB tester hardware control system improves the test speed of the PCB tester and simplifies the circuit design. In addition, due to the reconfigurable nature of FPGA, it has laid a good foundation for further optimization and upgrading of the system's software algorithms and hardware structure, and has good application prospects.


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