How to avoid EMI in PCB multilayer board design
There are many ways to solve EMI problems. Modern EMI suppression methods include: using EMI suppression coating, selecting appropriate EMI suppression parts and EMI simulation design. Starting from the most basic PCB layout, this paper discusses the function and design skills of PCB stacking in controlling EMI radiation.
The output voltage of IC will jump faster if the capacitor with proper capacity is placed near the power pin of IC. Due to the limited frequency response of the capacitor, it is impossible for the capacitor to generate the harmonic power needed to drive the IC output cleanly in the whole frequency band. In addition, the transient voltage formed on the power bus will form voltage drop at both ends of the inductance in the decoupling path. These transient voltages are the main common mode EMI interference sources.
As far as the IC on the circuit board is concerned, the power supply layer around the IC can be regarded as an excellent high-frequency capacitor, which can collect the part of energy leaked by the discrete capacitor that provides high-frequency energy for clean output. In addition, the inductance of the excellent power supply layer is smaller, so the transient signal synthesized by the inductance is smaller, and then the common mode EMI is reduced.
The connection between the power supply layer and the IC power supply pin must be as short as possible, because the rising edge of the digital signal is faster and faster, it is better to connect it directly to the pad where the IC power supply pin is located.
In order to control the common mode EMI, the power supply layer must be a pair of well-designed power supply layers in order to facilitate decoupling and have sufficiently low inductance. So, what kind of degree is good? The answer depends on the layering of the power supply, the materials between the layers, and the operating frequency (i.e., a function of IC rise time). In general, the spacing between power supply layers is 6mil, and the interlayer is made of FR4 material, so the equivalent capacitance per square inch of power supply layer is about 75pF. Obviously, the smaller the layer spacing, the larger the capacitance.
According to the current IC development speed, devices with rise time in the range of 100-300ps will occupy a high proportion. For circuits with a rise time of 100 to 300 PS, the 3 mil layer spacing is no longer applicable for most applications. At that time, it is necessary to use the delamination technology with the interlayer spacing less than 1 mil, and replace the FR4 dielectric material with the material with high dielectric constant. Now, ceramics and ceramic plastics can meet the design requirements of 100-300ps rise time circuit.
For today's common 1 to 3 ns rise time circuits, 3 to 6 mil layer spacing and FR4 dielectric materials, high-end harmonics can usually be processed and the transient signal can be low enough, that is to say, the common mode EMI can be reduced very low. In this paper, the design example of PCB layered stack will assume that the layer spacing is 3-6mil.
From the point of view of signal routing, a good layering strategy should be to put all signal routing on one or several layers, which are next to the power layer or ground layer. For the power supply, a good layering strategy should be that the power supply layer is adjacent to the ground plane, and the distance between the power supply layer and the ground plane should be as small as possible.
What stacking strategies can help shield and suppress EMI? The following layered stacking scheme assumes that the power supply current flows on a single layer and that single or multiple voltages are distributed in different parts of the same layer.
There are some potential problems in the design of the 4-layer board. First of all, the traditional four layer board with a thickness of 62 mil, even if the signal layer is in the outer layer and the power and ground layers are in the inner layer, the distance between the power and ground layers is still too large.
If the cost requirement is the first, two alternatives to the traditional 4-layer board can be considered. Both of these schemes can improve the EMI suppression performance, but they are only suitable for the situation where the density of the components on the board is low enough and there is enough area around the components (to place the required copper-clad layer of the power supply).
The first is the preferred scheme. The outer layer of PCB is the layer, and the middle two layers are the signal / power layer. The power supply on the signal layer is routed by a wide line, which makes the path impedance of the power supply current low and that of the signal microstrip path low. From the perspective of EMI control, this is the best 4-layer PCB structure available.
In the second scheme, the outer layer goes to power and ground, and the middle two layers go to signal. Compared with the traditional 4-layer board, the improvement is smaller, and the interlayer impedance is as poor as the traditional 4-layer board.
If you want to control the routing impedance, the above stacking scheme should be very careful to arrange the routing under the power supply and the grounding copper island. In addition, the copper laying islands on the power supply or stratum shall be interconnected as much as possible to ensure the DC and low frequency connectivity.
If the element density on the 4-layer board is relatively large, it is better to use the 6-layer board. However, in the 6-layer board design, some lamination schemes have not good shielding effect on electromagnetic field, and have little effect on reducing the transient signal of power bus. Here are two examples:
In the first case, the power supply and ground are placed on the second and fifth layers respectively. Because of the high copper-clad impedance of the power supply, it is very unfavorable to control the common mode EMI radiation. However, from the point of view of signal impedance control, this method is very correct.
In the second example, the power supply and ground are placed on the third and fourth layers respectively. This design solves the problem of copper-clad impedance of the power supply. Due to the poor electromagnetic shielding performance of the first and sixth layers, the differential mode EMI is increased. If the number of signal lines on the two outer layers is the least and the length of the line is very short (less than 1 / 20 of the maximum harmonic wavelength of the signal), this design can solve the problem of differential mode EMI. The difference mode EMI can be suppressed very well by filling the non component and non wiring areas on the outer layer with copper and grounding the copper covered areas (every 1 / 20 wavelength is interval). As mentioned before, the copper laying area shall be connected with the internal ground plane at multiple points.
Generally, the first and sixth layers are distributed as strata, and the third and fourth layers are distributed as power and ground. Because there are two middle layers of dual microstrip signal line between the power layer and the ground layer, the EMI suppression ability is excellent. The disadvantage of this design is that there are only two layers in the routing layer. As mentioned earlier, if the outer layer has short routing and copper is laid in the area without routing, the same stacking can be realized with the traditional 6-layer board.
Another 6-layer board layout is signal, ground, signal, power, ground and signal, which can achieve the environment required for high-level signal integrity design. The signal layer is adjacent to the ground plane, and the power layer is matched with the ground plane. Obviously, the disadvantage is that the stacking of layers is unbalanced.
This usually causes trouble for processing and manufacturing. The solution is to fill all blank areas of the third layer with copper. After copper filling, if the copper density of the third layer is close to the power layer or the ground plane, the board can not be strictly counted as a circuit board with balanced structure. The copper filling area must be connected to power or ground. The distance between connecting vias is still 1 / 20 wavelength. It is not necessary to connect them everywhere, but it should be connected ideally.
10 ply board
Due to the thin insulation layer between multi-layer boards, the impedance between 10 or 12 layer boards is very low. As long as there is no problem in layering and stacking, excellent signal integrity can be expected. It is more difficult to manufacture 12 ply plates according to the thickness of 62 mil, and few manufacturers can process 12 ply plates.
Since there is always an insulating layer between the signal layer and the loop layer, the scheme of allocating the middle 6 layers to route the signal line in the 10 layer board design is not the best. In addition, it is important to make the signal layer adjacent to the loop layer, that is, the board layout is signal, ground, signal, signal, power, ground, signal, signal, ground, signal.
This design provides a good path for signal current and its loop current. The proper routing strategy is that the first layer runs in the X direction, the third layer in the Y direction, the fourth layer in the X direction, and so on. Visually, layer 1 and layer 3 are a pair of layered combinations, layer 4 and layer 7 are a pair of layered combinations, and layer 8 and layer 10 are the last pair of layered combinations. When it is necessary to change the routing direction, the signal line on the first layer shall change the direction after going through the hole to the third layer. In fact, this may not always be the case, but as a design concept, we should try to comply with it.
Similarly, when the direction of signal routing changes, it should be from layer 8 and layer 10 or from layer 4 to layer 7 by vias. This routing ensures the most tight coupling between the forward path and the loop of the signal. For example, if the signal is routed on the first layer, and the loop is routed on the second layer and only on the second layer, then even if the signal on the first layer is transferred to the third layer through the hole, the loop is still on the second layer, so as to maintain the characteristics of low inductance, large capacitance and good electromagnetic shielding performance.
What if the actual route is not like this? For example, when the signal wire on the first layer passes through the via to the 10th layer, the loop signal has to look for the grounding plane from the 9th layer, and the loop current needs to find the nearest grounding via (such as the grounding pin of resistance or capacitance and other components). If it happens that there are such vias nearby, it's really lucky. If there is no such near via available, the inductance will increase, the capacitance will decrease, and the EMI will certainly increase.
When the signal line must leave the current pair of wiring layers through the vias to other wiring layers, the grounding vias should be placed near the vias, so that the loop signal can smoothly return to the appropriate ground plane. For layer 4 and layer 7 layered combination, the signal loop will return from the power layer or ground layer (i.e. layer 5 or layer 6), because the capacitance coupling between the power layer and ground layer is good and the signal is easy to transmit.
Design of multi power supply layer
If two power supply layers of the same voltage source need to output large current, the circuit board shall be arranged into two groups of power supply layers and ground layers. In this case, an insulating layer is placed between each pair of power supply layers and the ground plane. In this way, we can get two pairs of power busbars with equal impedance. If the stack of power layers causes unequal impedance, the shunt will be uneven, the transient voltage will be much larger, and EMI will increase dramatically.
If there are multiple power supply voltages with different values on the circuit board, multiple power supply layers are required accordingly, and it is important to keep in mind to create a pair of power supply layers and ground layers for different power supplies. In both cases, when determining the location of the mating power and ground layers on the circuit board, remember the manufacturer's requirements for the balanced structure.
In circuit board design, thickness, through-hole process and the number of layers of circuit board are not the key to solve the problem. Excellent layer stacking is the key to ensure the bypass and decoupling of power bus, minimize the transient voltage on the power layer or ground layer, and shield the signal and the electromagnetic field of power supply. reason