Next-generation system design makes packaging and PCB design easier
In most cases, modern electronic system design involves designing various components or systems that are relatively isolated from each other. The design of the IC and the pin output are determined by the position of the circuit on the chip. Package designers use "throw-to-wall" chip designs, and design the shortest package bond wires as possible to keep the package as small as possible. Then PCB designers usually complain all the time, pick up the packaged IC, and rack their brains to find out how to route signals, which always seems to be misplaced on a certain pin or solder ball.
With the increasing complexity of SoCs and the development of multi-chip packaging, companies have begun to realize the value of cross-domain collaboration between ICs, packaging substrates, and PCB design groups. Due to the cost-sensitivity of high-pin-count devices, engineers have to rethink how to plan and optimize the chip's I / O layout while compromising complex IC package variables. And do all this for multiple board-level platforms. The advent of tools now makes packaging and PCB design a collaborative and mutually beneficial process.
To be most effective, EDA tools should be aware of tools that will be used in other processes. In the areas of packaging and PCB design, little is known about each other. It is true that FPGA pin outputs can be user-defined within a certain range, but "standard" components generally do not have such options.
Let the tools clear the design and product design to other links in the process flow, these tools can cooperate in a shorter time and deliver better system design. In addition, standard IC chips can be packaged in different ways, depending on the form factor of the end product, enabling more optimized solutions for various ways.
How can tools quickly recognize each other and then collaborate to deliver a better design? The design of smartphones and tablets using the same CPU chip perfectly illustrates this pattern. Obviously, many mobile device companies are making such an attempt.
However, compared to smart phones, the usable area on the PCB substrate of tablet PCs is obviously larger and its constraints are less. As a result, the CPU package on a tablet may be larger, have different pin outputs, or may consume more power than the CPU on a smartphone. Therefore, a single "standard" package may not be the best application package (Figure 1).
Tablet PC design may have more available board area layout CPU and glue circuit
Figure 1: Tablet PC designs may have more usable substrate area layout CPUs and glued circuits to allow the upper package to function. However, for smart phones using the same CPU, this approach requires too much space, so a better solution is to use lower-level packaging.
Now, with the new tools, designers can configure the chip, “see” the design from a packaging perspective, and then move to PCB (traditional method), or understand the PCB design requirements before returning to the package design. Moreover, they can get every product that uses this CPU, and then go back to the PCB to design the best package specifically optimized for this design.
From a packaging perspective, the physical design rules are determined by the PCB design requirements. The tool then interacts with rule and packaging designers to deliver the best package for the specific application of the chip. This relatively fast package design approach also explores different ideas to quickly find the best solution.
real case scenario
Figure 2 is a hypothetical product design. In this example, the shape parameters of the final product are known, and the components have been initially laid out. Note the instructions at the top, where the CPU has been reserved. Using this input, the tool can begin path finding by trying multiple package configurations based on rules written by PCB designers and package designers.
Physical shape parameters are the main constraints of product design
Figure 2: In general, physical form factors are the main constraints on product design. Using path finding tools, package and PCB designers can collaborate to find the best package within the physical design constraints and simplify fanout and routing of complex packages.
For each design, traditional routing can be performed on the PCB to determine the best package and pin output. The rules allow designers to define various parameters such as unused output corner pins, how to connect differential pairs together, how to allocate power and ground, and how to handle data and address buses.
Once the rules are determined, it's not just "press the button and sit back", but it's more direct, faster, and more accurate than using a spreadsheet and pin list.
Tool-aware design has significant advantages, and it can be optimized in any design field. First, it makes it easier to customize multiple package designs to make optimal use of a given component to the required form factor. Then look at the design from multiple "what-if" scenarios, such as smaller packages, less cost, the simplest fan-out and exit. Second, due to the large number of pins, package designs using spreadsheets and pin lists can be overwhelming. When manually inputting hundreds of pin data, the error rate is almost 100%. Of course, the advantages also include: improved quality, obtaining the best package suitable for the form factor, reduction of errors, and significant time savings in the overall system design.