Optimal design of power integrity in high-speed printed circuit boards
Abstract: With the widespread application of large-scale digital integrated circuits such as DSP and FPGA on air-to-air missile high-speed image information processing boards, the frequency of signals is also getting higher and higher, and the image information processing board has a problem of large voltage drop. When the frequency is low, the power and ground can be used as a complete reference plane, and the power supply voltage drop is small. However, at high frequencies, due to the influence of the distributed inductance ESL, the power supply and ground plane are equivalent to a resonant cavity and have resonance characteristics. The power plane can be seen as a network of more inductors and capacitors, or a resonant cavity. At a certain frequency, these capacitors and inductors will resonate, which will affect the impedance of the power layer. With the increase of frequency, the impedance of the power source is constantly changing, especially when the parallel resonance effect is significant, the impedance of the power source is also obvious, so a certain voltage drop and voltage swing will occur when the instantaneous current passes. However, most digital circuit devices require power supply fluctuations within the range of ± 5% of the normal voltage, so that digital circuit devices cannot work properly.
This paper combines the theory of power supply integrity with PCB design examples, and optimizes the design of power supply integrity in terms of resonance, power supply impedance, avoiding the division of important signal lines across plane layers, and DC voltage drop.
1 Optimize PCB layout by resonance analysis
Resonant mode calculation analyzes the risks that may be caused by the structure of the power and ground in the PCB, including stacking, plate, and ground electrical division. The purpose is to prevent the printed circuit board from resonating in the frequency range of interest.
Observe the voltage distribution in the PCB's resonance mode, and try to avoid placing high current ICs at or near the resonance position. The resonance diagram of the power and ground on the image information processing board is shown in Figure 1.
It can be seen from the figure that the upper-right corner of the printed circuit board has a large resonance, so the high-current IC device should be placed in the upper-right corner of the printed board as much as possible when the printed circuit board is laid out.
2 Optimized circuit design for reducing impedance of power supply
The quality of the system power supply directly affects the stability of the system, and may even make the system logic wrong. A low-impedance power distribution system is ideal, at least showing low impedance in the operating frequency band of the entire system, thereby having a smaller voltage drop. Taking the FPGA on the image processing board as an example, the power supply is 3.3 V, the voltage noise limit is 5%, and the maximum instantaneous current is 0.15 A. The maximum power impedance of the design is shown in formula (1)
The power impedance simulation is performed on the 3.3 V power supply of the FPGA. Figure 2 shows the 3.3 V power supply impedance of the FPGA.
Figure 2 3.3V power supply impedance of FPGA
It can be seen from the figure that the impedance at the resonance frequency points is high at 357 MHz and 765 MHz, and a suitable decoupling capacitor needs to be selected to improve the impedance characteristic of the power supply. Here, a capacitor with a capacitance of 200 pF and packaged as 0603 is selected as the decoupling capacitor of the FPGA, because its characteristic curve is consistent with the peak frequency of the power supply impedance curve, which can reduce the peak value of the power supply impedance.
The layout of the 200 pF decoupling capacitor is selected at the position where the resonance voltage fluctuates the most at 357 MHz. Because the resonance is obvious here, the power impedance at the resonance frequency is also high at 728 MHz, so two 62 pF capacitors are added. After that, the power supply impedance is shown by the solid line in Fig. 3, and the dotted line is the power supply impedance with no capacitor added initially.
Figure 3 Comparison of power supply impedance after final optimization
As can be seen from Figure 3, the impedance of the power supply has been greatly improved, meeting the requirements below the maximum power supply impedance.
3 Avoid high-speed signal lines split across plane layers
Power and ground division, line width, and vias will cause discontinuities in the impedance of the PCB transmission line, causing unsatisfactory power plane and ground plane return paths, and causing power integrity issues. In order to obtain better signal quality, the line width and the thickness of the dielectric layer, and the dividing lines of the power and ground can be adjusted to meet the requirements of characteristic impedance. Take FPGA_CLK as an example. In the current PCB, the transmission line impedance is shown in Figure 4. The impedance fluctuates between 43.5 and 54.7 Ω, and the fluctuation is too large.
In order to improve the characteristics of the transmission line, PCB layering is optimized. By adjusting the line width, the thickness of the dielectric layer, and not splitting across the plane layer, etc. to meet the 50 Ω characteristic impedance requirements. The optimized transmission line impedance is shown in Figure 5.
After the FPGA_CLK is optimized in the stacked structure, the transmission line impedance is between 49.5 and 50.5 Ω, which meets the requirements of impedance matching. The power ground network and the signal network are not separated, but are tightly coupled together, so the noise of the power ground will also affect the signal line through the coupling or radiate to the outside, which will cause EMI and EMC problems. By contrast in electromagnetic radiation. Figure 6 shows the waveform of electromagnetic radiation without optimization, and Figure 7 shows the waveform of electromagnetic radiation after optimization.
Through comparison in the figure, electromagnetic radiation is significantly reduced.
4 DC voltage drop
PCB In PCB design, due to the division of the plane layer, the undesired current path and the distribution of various via signal lines, the DC power supply of the power network is often affected. DC voltage drop analysis can show the current flow, circuit density, and DC voltage drop characteristics on the entire PCB.
Set the current source and voltage source at the exit of the chip that generates 3.3 V, and place the probe of the current source and the probe of the voltage source at the upper right of the printed board, as shown in Figure 8.
It can be seen that the dark area indicates that the current density is too large, and the red is more obvious at the two DSPs. The size of the isolation disk can be reduced to allow the current to pass. At the 3.3 V power supply, the size of the via hole can be increased and a few more A via method allows current to flow in several places to reduce the density of the current. Then do voltage and voltage drop simulation, the simulation diagram is shown in Figure 9.
The minimum voltage is 3.285 V, and the voltage drop is 0.5%, which meets the requirement of system voltage fluctuation within ± 10%.
5 Concluding remarks
Power integrity problems are mainly caused by problems such as irrational design of decoupling capacitors, severe loop effects, poor division of multiple power / ground planes, irrational ground plane design, and uneven current. Find these problems through power integrity simulation, and then solve the power integrity problems by: (1) Adjusting the PCB stackup line width and dielectric layer thickness to meet the characteristic impedance requirements, and adjusting the stacking structure to meet the signal line return path The short principle adjusts the division of the power supply / ground plane to avoid the phenomenon of cross division of important signal lines; (2) The power supply impedance analysis of the power supply used on the printed board is performed, and the target impedance is controlled by adding a capacitor (3) Adjust the position of the device in the part with high current density to make the current pass through a wider path.