SAR ADC PCB layout: reference path

- Jan 14, 2020-

SAR ADC PCB layout: reference path


When designing a high-performance data acquisition system, diligent engineers carefully select a high-precision ADC, as well as other components needed for analog front-end regulating circuit. After several weeks of design work, the simulation and optimization of the circuit schematic diagram are carried out. In order to catch up with the construction period, the designers quickly combine the layout and wiring of the circuit board together. A week later, the first prototype circuit board was tested. Unexpectedly, the performance of the circuit board is not the same as expected.

Has this happened to you?

The optimal PCB layout is very important for ADC to achieve the expected performance. When designing circuits that contain mixed signal devices, you should always start with good grounding arrangements and use the best placement of components and signal routing routing to divide the design into analog, digital, and power parts.


The reference path is the most critical in ADC layout and routing because all transitions are a function of the reference voltage. In the traditional SAR ADC architecture, the reference path is also the most sensitive, because there will be a dynamic load to the reference source on the reference pin.


Since the reference voltage is sampled several times during each conversion, high current transients appear at this terminal, where the ADC internal capacitor array is turned on and charged at this position. The reference voltage must be stable in each conversion clock cycle, and stable to the required n-bit resolution, otherwise there will be linear error and code loss error.


Figure 1 shows the current transients during the transition phase on a typical 12 bit SAR ADC reference terminal.



Figure 1 current transients on 12 bit SAR ADC reference pins


Due to these dynamic currents, a high quality bypass capacitor (CREF) is required to decouple the reference pins. The bypass capacitor is used as a charge memory to provide instantaneous charging during these high frequency transient currents. You should place the reference bypass capacitors as close to the reference pins as possible and connect them together using a short low inductance connection.


Figure 2 shows an example of board layout and wiring for a 14 bit dual ADC with two independent voltage references for ads7851.


Figure 2 example of dual ADC layout wiring with two independent internal voltage references


In this four layer PCB example, the designer uses a solid ground plane directly below the device, and divides the circuit board into analog and digital parts to keep the sensitive input and reference signal away from the noise source. He bypassed the refout-a and refout-b reference outputs with a 10 μ F, X7R, size 0805 ceramic capacitor (cref-x) to achieve optimal performance and connected them to devices using a small 0.1 Ω series resistor to maintain a constant impedance at overall low and high frequencies. He also uses wide traces to reduce inductance.

I strongly recommend placing CREF on the same layer as ADC. You should also avoid placing pilot holes between the reference pin and the bypass capacitor. Each reference ground pin of ads7851 has a separate ground connection, and each bypass capacitor has a separate inductive connection to the ground path.


If you are using an ADC that requires an external reference source, you should minimize the inductance in the reference signal path - the starting point of this path is the reference buffer output to the bypass capacitor until the ADC reference input.


Figure 3 shows an example of an 18 bit, SAR, ADC ads8881 layout using an external reference and buffer. By placing the capacitor within 0.1 inch of the pin and connecting it to a 20 mil wide trace and multiple 15 mil size ground pilot holes, the designer keeps the inductance between the reference capacitor and the ref pin at less than 2nh. I recommend a single, 10uF, X7R, size 0805 ceramic capacitor with a rated voltage of at least 10V.


The trace length from the reference buffer circuit to the ref pin is kept as short as possible to ensure fast and stable response.


The correct decoupling of ref pin is very important to achieve optimal performance. In addition, maintaining a low inductive connection in the reference path keeps the reference drive circuit stable during the conversion, which takes you one step further to achieve the desired effect.


Figure 3 example of ADC layout with an external reference and buffer

If you want to delve into this topic, please check the layout and routing guide in the ads8881 and ads7851 datasheets.

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