A-Signal integrity--Chip-to-chip signal integrity-pcb

- Feb 07, 2017-

Signal integrity--Chip-to-chip signal


Chip-to-chip signal integrity

For wired connections, it is important to compare the interconnect flight time to the bit period to decide whether an impedance matched or unmatched connection is needed.

The channel flight time (delay) of the interconnect is roughly 1 ns per 15 cm (6 in) of FR-4 stripline (the propagation velocity depends on the dielectric and the geometry). Reflections of previous pulses at impedance mismatches die down after a few bounces up and down the line (i.e. on the order of the flight time). At low bit rates, the echoes die down on their own, and by midpulse, they are not a concern. Impedance matching is neither necessary nor desirable. There are many circuit board types other than FR-4, but usually they are more costly to manufacture.

The gentle trend to higher bit rates accelerated dramatically in 2004, with the introduction by Intel of the PCI-Express standard. Following this lead, the majority of chip-to-chip connection standards underwent an architectural shift from parallel buses to serializer/deserializer (SERDES) links called "lanes." Such serial links eliminate parallel bus clock skew and reduce the number of traces and resultant coupling effects but these advantages come at the cost of a large increase in bit rate on the lanes, and shorter bit periods.

At multigigabit/s data rates, link designers must consider reflections at impedance changes (e.g. where traces change levels at vias), noise induced by densely packed neighboring connections (crosstalk), and high-frequency attenuation caused by the skin effect in the metal trace and dielectric loss tangent. Examples of mitigation techniques for these impairments are a redesign of the via geometry to ensure an impedance match, use of differential signaling, and preemphasis filtering, respectively.

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