Signal integrity-Finding IC signal integrity
Finding IC signal integrity problems
Typically, an IC designer would take the following steps for SI verification:
Perform a layout extraction to get the parasitics associated with the layout. Usually worst-case parasitics and best-case parasitics are extracted and used in the simulations. For ICs, unlike PCBs, physical measurement of the parasitics is almost never done, since in-situ measurements with external equipment are extremely difficult. Furthermore, any measurement would occur after the chip has been created, which is too late to fix any problems observed.
Create a list of expected noise events, including different types of noise, such as coupling and charge sharing.
Create a model for each noise event. It is critical that the model be as accurate as possible.
For each signal event, decide how to excite the circuit so that the noise event will occur.
Create a SPICE (or another circuit simulator) netlist that represents the desired excitation, to include as many effects (such as parasitic inductance and capacitance, and various distortion effects) as possible.
Run SPICE simulations. Analyze the simulation results and decide whether any re-design is required. It is common to analyze the results with an eye pattern and by calculating a timing budget.
Modern signal integrity tools for IC design perform all these steps automatically, producing reports that give a design a clean bill of health, or a list of problems that must be fixed. However, such tools generally are not applied across an entire IC, but only selected signals of interest.