DDR4 SDRAM-History-circuit board pcb
Standards body JEDEC began working on a successor to DDR3 around 2005, about 2 years before the launch of DDR3 in 2007. The high-level architecture of DDR4 was planned for completion in 2008.
Some advance information was published in 2007, and a guest speaker from Qimonda provided further public details in a presentation at the August 2008 San Francisco Intel Developer Forum (IDF). DDR4 was described as involving a 30 nm process at 1.2 volts, with bus frequencies of 2133 MT/s "regular" speed and 3200 MT/s "enthusiast" speed, and reaching market in 2012, before transitioning to 1 volt in 2013.
Subsequently, further details were revealed at MemCon 2010, Tokyo (a computer memory industry event), at which a presentation by a JEDEC director titled "Time to rethink DDR4" with a slide titled "New roadmap: More realistic roadmap is 2015" led some websites to report that the introduction of DDR4 was probably or definitely delayed until 2015. However, DDR4 test samples were announced in line with the original schedule in early 2011 at which time manufacturers began to advise that large scale commercial production and release to market was scheduled for 2012.
DDR4 was expected to represent 5% of the DRAM market in 2013, and to reach mass market adoption and 50% market penetration around 2015; as of 2013, however, adoption of DDR4 has been delayed and it is no longer expected to reach a majority of the market until 2016 or later. The transition from DDR3 to DDR4 is thus taking longer than the approximately five years taken for DDR3 to achieve mass market transition over DDR2. In part, this is because changes required to other components would affect all other parts of computer systems, which would need to be updated to work with DDR4.
In February 2009, Samsung validated 40 nm DRAM chips, considered a "significant step" towards DDR4 development since in 2009, DRAM chips were only beginning to migrate to a 50 nm process. In January 2011, Samsung announced the completion and release for testing of a 2 GiB DDR4 DRAM module based on a process between 30 and 39 nm. It has a maximum data transfer rate of 2133 MT/s at 1.2 V, uses pseudo open drain technology (adapted from graphics DDR memory) and draws 40% less power than an equivalent DDR3 module.
In April 2011, Hynix announced the production of 2 GiB DDR4 modules at 2400 MT/s, also running at 1.2 V on a process between 30 and 39 nm (exact process unspecified),adding that it anticipated commencing high volume production in the second half of 2012. Semiconductor processes for DDR4 are expected to transition to sub-30 nm at some point between late 2012 and 2014.
In May 2012, Micron announced it is aiming at starting production in late 2012 of 30 nm modules.
In July 2012, Samsung Electronics Co., Ltd., announced that it has begun sampling the industry's first 16 GiB registered dual inline memory modules (RDIMMs) using DDR4 SDRAM for enterprise server systems.
In September 2012, JEDEC released the final specification of DDR4.
In April 2014, Hynix announced that it has developed the world's first highest-density 128 GiB module based on 8 Gib DDR4 using 20 nm technology. The module works at 2133 MHz, with a 64-bit I/O, and processes up to 17 GB of data per second. Hynix expects DDR4 SDRAM to be commercialized by 2015, and turned into a standard by 2016.
In April 2016, Samsung announced that they had begun to mass-produce DRAM on a "10nm-class" process, by which they mean the 1xnm node regime of 16 nm to 19 nm, which supports a 30% faster data transfer rate of 3,200 megabits per second. Previously, a size 20 nm was used.